Semiconductor device and method of manufacturing the same

ABSTRACT

A semiconductor device and a method of manufacturing the same. The semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region within the first well, and a third well formed within the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.

BACKGROUND

1. Field of the Invention

The invention relates in general to a semiconductor device and a methodof manufacturing the same and, more particularly, to a semiconductordevice and a method of manufacturing the same, wherein leakage currentoccurring due to a parasitic bipolar transistor by a triple wellstructure at the time of erasure can be prevented.

2. Discussion of Related Art

An NAND flash memory device performs data program by injecting electronsinto the floating gate by Fowler-Nordheim (FN) tunneling. The NAND flashmemory device provides a large capacity and a high level of integration.

The NAND flash memory device includes a number of cell blocks. Each cellblock includes a number of cell strings in which a number of cells forstoring data are connected in series to form one string, and a drainselect transistor and a source select transistor formed between the cellstring and the drain, and the cell string and the source, respectively.Each cell block further includes a peri region in which a number ofcircuit elements for generating a predetermined bias for the program,erasure, and read operations of a cell and transferring the bias areformed.

Furthermore, cells that constitute different cell strings and are drivenby the same word line (WL) form a page. Gates of a number of drainselect transistors are commonly connected to a drain select line (DSL)and are driven by the potential of the drain select line. Gates of anumber of source select transistors are commonly connected to a sourceselect line and are driven by the potential of the source select line.

The NAND flash memory cell includes a gate in which a tunnel oxidelayer, a floating gate, a dielectric layer, and a control gate arelaminated in a predetermined region of a semiconductor substrate, and ajunction formed on the semiconductor substrate at both sides of thegate.

A NAND flash memory device constructed as described above is anelectrically programmable and erasable device, and it performs programand erase functions in such a manner that electrons vary the thresholdvoltage while being moved due to a strong electric field through a thintunnel oxide layer.

The NAND flash memory device implements erasure on a block basis. Forthe purpose of erasure, it is necessary that a ground voltage (Vss) beapplied to the entire word lines of a selected cell block and a highvoltage of about 20 V be applied to the well.

As described above, the NAND flash memory device performs the erasureoperation by applying a high voltage typically of about 20 V, to thewell. Accordingly, the semiconductor substrate of the cell region musthave a triple well structure. That is, an N well is formed on a P-typesemiconductor substrate and a P well is formed on an N well, therebyforming the triple well structure. In this case, a parasitic bipolartransistor is formed between the semiconductor substrate, the N well,and the P well.

The parasitic bipolar transistor keeps turned off with a high voltagenot being applied to the well. However, if a high voltage of about 20 Vis applied to the well for erasure, the parasitic bipolar transistor isturned on and the leakage current is generated accordingly. Moreparticularly, a great amount of leakage current is generated at theboundary of the cell region and the peri region. The leakage currentcauses to drop an erase voltage, resulting in the failure of the eraseoperation.

SUMMARY OF THE INVENTION

In one embodiment, the invention relates to a semiconductor device and amethod of manufacturing the same, wherein drop of an erase voltage,which is incurred by the leakage current between the cell region and theperi region due to the parasitic bipolar transistor at the time oferasure can be prevented.

The semiconductor substrate of the cell region has multiple wells oftriple or more wells. More particularly, the P well is further formed inthe N well, forming the well of a PNPN structure. If so, a breakdownvoltage can be increased compared with an existing PNP structure, theleakage current can be reduced, and the drop of an erase voltage can beprevented.

A semiconductor device according to one aspect of the invention includesa first well formed in a predetermined region of a semiconductorsubstrate, a second well formed in a predetermined region within thefirst well, and a third well formed within the first well with the thirdwell being spaced apart from the second well at a predetermineddistance. A multiple well of the semiconductor substrate, the firstwell, the second well, the first well, and the third well, which aresequentially disposed, is formed.

The first well may preferably be formed using an N-type impurity, andthe second well and the third well may preferably be formed using aP-type impurity.

According to another aspect, the invention provides a method ofmanufacturing a semiconductor device, including the steps of injecting apredetermined impurity ion into a predetermined region of asemiconductor substrate, forming a first well, etching a predeterminedregion of the semiconductor substrate in which the first well is formed,forming a trench, gap-filling the trench with a polysilicon layer,forming an impurity region in a predetermined region within the firstwell so that the impurity region is connected to the polysilicon layer,forming a second well including the polysilicon layer and the impurityregion, and performing a predetermined impurity ion implantation processto form a third well in a predetermined region within the first well sothat the third well is spaced apart from the second well at apredetermined distance.

The first well may preferably be formed by injecting an N-type impurity.

The method may preferably further include the step of performing anannealing process after the trench is formed.

The annealing process may preferably be performed under a nitrogenatmosphere.

The annealing process may preferably be performed at a temperature of850° C. to 100° C. for 30 minutes to 60 minutes.

The polysilicon layer may preferably be doped with a P-type impurity.

The impurity region may preferably be formed by injecting a P-typeimpurity and then performing an nitrogen annealing process so that theimpurity region is connected to the bottom of the polysilicon layer.

The third well may preferably be formed by injecting a P-type impurity.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings in which likereference symbols indicate the same or similar components, wherein:

FIG. 1 is a cross-sectional view of a semiconductor device according toan embodiment of the invention; and

FIGS. 2A to 2E are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of theinvention.

DETAILED DESCRIPTION OF EMBODIMENTS

The invention will now be described in detail in connection with certainexemplary embodiments with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a semiconductor device according toan embodiment of the invention.

An N-type first well 20 is formed on a P-type semiconductor substrate10. A P-type second well 30 is formed within the first well 20. A P-typethird well 40 is formed within the first well 20 with the first well 20being intervened between the P-type third well 40 and the second well30. Accordingly, a multiple well structure of the semiconductorsubstrate 10, the first well 20, the second well 30, the first well 20,and the third well 40, which are sequentially disposed, is formed.

FIGS. 2A to 2E are cross-sectional views illustrating a method ofmanufacturing a semiconductor device according to an embodiment of theinvention.

Referring to FIG. 2A, a first photoresist layer (not shown) is formed ona semiconductor substrate 11. The first photoresist layer (not shown) ispatterned by photolithography and development processes employing a maskthrough which a predetermined region (for example, a cell region) of thesemiconductor substrate 11 is exposed. Accordingly, the semiconductorsubstrate 11 of the cell region is exposed.

An N-type impurity (for example, phosphorous (P) ion) is then injectedwith a predetermined energy and dose to form a first well 12. In otherwords, the first well 12 is formed by injecting the N-type impurity intothe cell region of the semiconductor substrate 11.

Referring to FIG. 2B, an oxide layer 13 and a nitride layer 14 areformed on the semiconductor substrate 11 on which the first well 12 isformed. A second photoresist layer (not shown) is formed on the nitridelayer 14. The second photoresist layer (not shown) is patterned byphotolithography and development processes using a predetermined mask.The second photoresist layer (not shown) causes the nitride layer 14 ofa location at which the first well 12 is formed to be exposed such thata predetermined region of the semiconductor substrate 11 on which thefirst well 12 is formed is etched in a subsequent etch process.

The nitride layer 14 and the oxide layer 13 are etched using thepatterned second photoresist layer (not shown) as a mask. Thesemiconductor substrate 11 on which the first well 12 is formed isetched to predetermined width and depth, thus forming a trench 15.

Referring to FIG. 2C, after the second photoresist layer (not shown) isstripped, an annealing process for removing dangling bonds of silicon isimplemented. The annealing process may preferably be performed at atemperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30minutes to one hour. A polysilicon layer 16 is formed on the entiresurface so that the trench 15 is gap filled. The polysilicon layer 16may be one doped with a P-type ion (for example, boron (B) ion) having aconcentration of 10E17 ions/cm³ to 10E20 ions/cm³.

Referring to FIG. 2D, the oxide layer 13, the nitride layer 14, and thepolysilicon layer 16 remaining on the semiconductor substrate 11 arestripped. The nitride layer 14 may be stripped using any suitable means,such as phosphoric acid (H₃PO₄) and the oxide layer 13 may be strippedusing HF, for example.

After a third photoresist layer (not shown) is formed on the entiresurface, it is patterned by photolithography and development processesusing a predetermined mask. The third photoresist layer (not shown) ispatterned such that the first well 12 within the trench 15 in which thepolysilicon layer 16 is formed is exposed.

A P-type ion (preferably, the same ion (for example, boron (B) ion) asthat doped into the polysilicon layer 16) is injected with energy of 200to 500 keV and dose of 1.0E12 ions/cm² to 5.0E14 ions/cm². An annealingprocess is then performed to form an impurity region 17 within the firstwell 12. The annealing process may preferably be performed at atemperature of 850° C. to 1100° C. under a nitrogen atmosphere for 30minutes to one hour.

If so, the impurity region 17 is connected to the bottom of thepolysilicon layer 16. Accordingly, the polysilicon layer 16 and theimpurity region 17 constitutes a P-type second well 18 and the firstwell 12 is divided by the P-type second well 18.

Referring to FIG. 2E, after the third photoresist layer (not shown) isstripped, a fourth photoresist layer (not shown) is formed on the entiresurface. The fourth photoresist layer (not shown) is patterned byphotolithography and development processes using a predetermined mask.The fourth photoresist layer (not shown) is patterned so that apredetermined region of the first well 12 is exposed with it being apartspaced from the second well 18 at a predetermined distance.

A P-type impurity (for example, boron (B) ion) is injected using thefourth photoresist layer (not shown) as a mask, forming a third well 19.After the fourth photoresist layer (not shown) is stripped, a subsequentprocess is performed.

As described above, in the NAND flash memory device according to theinvention, the semiconductor substrate is formed to have a multiple wellstructure of triple or more. Accordingly, a breakdown voltage can beincreased and a leakage current can be reduced. It is therefore possibleto prevent the drop of an erase voltage and to reduce the error of anerase operation.

While the invention has been described in connection with practicalexemplary embodiments, the invention is not limited to the disclosedembodiments but, to the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

1. A semiconductor device, comprising: a first well formed in apredetermined region of a semiconductor substrate; a second well formedin a predetermined region within the first well; and a third well formedwithin the first well with the third well being spaced apart from thesecond well at a predetermined distance, whereby a multiple well of thesemiconductor substrate comprising the sequentially formed the firstwell and second well, and the sequentially formed first well and thirdwell, is formed.
 2. The semiconductor device of claim 1, wherein thefirst well is formed using an N-type impurity, and the second well andthe third well are formed using a P-type impurity.
 3. A method ofmanufacturing a semiconductor device, the method comprising the stepsof: injecting a predetermined impurity ion into a predetermined regionof a semiconductor substrate, forming a first well; etching apredetermined region of the semiconductor substrate in which the firstwell is formed, forming a trench; gap-filling the trench with apolysilicon layer; forming an impurity region in a predetermined regionwithin the first well so that the impurity region is connected to thepolysilicon layer, forming a second well comprising the polysiliconlayer and the impurity region; and performing a predetermined impurityion implantation process to form a third well in a predetermined regionwithin the first well so that the third well is spaced apart from thesecond well at a predetermined distance.
 4. The method of claim 3,comprising forming the first well by injecting an N-type impurity. 5.The method of claim 3, further comprising the step of performing anannealing process after forming the trench.
 6. The method of claim 5,comprising performing the annealing process under a nitrogen atmosphere.7. The method of claim 5, comprising performing the annealing process ata temperature of 850° C. to 1100° C. for 30 minutes to 60 minutes. 8.The method of claim 3, comprising doping the polysilicon layer with aP-type impurity.
 9. The method of claim 3, comprising forming theimpurity region is formed by injecting a P-type impurity and thenperforming an nitrogen annealing process so that the impurity region isconnected to the bottom of the polysilicon layer.
 10. The method ofclaim 3, comprising forming the third well by injecting a P-typeimpurity.